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74F181 4-Bit Arithmetic Logic Unit
April 1988 Revised July 1999
74F181 4-Bit Arithmetic Logic Unit
General Description
The 74F181 is a 4-bit Arithmetic logic Unit (ALU) which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations. It is 40% faster than the Schottky ALU and only consumes 30% as much power.
Features
s Full lookahead for high-speed arithmetic operation on long words
Ordering Code:
Order Number 74F181SC 74F181PC 74F181SPC Package Number M24B N24A N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Active-HIGH Operands
Connection Diagram
Active-LOW Operands
IEEE/IEC
(c) 1999 Fairchild Semiconductor Corporation
DS009491
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74F181
Unit Loading/Fan Out
U.L. Pin Names A0-A3 B0-B3 S0-S3 M Cn F0-F3 A=B G P Cn + 4
Note 1: OC-Open Collector
Description HIGH/LOW A Operand Inputs (Active LOW) B Operand Inputs (Active LOW) Function Select Inputs Mode Control Input Carry Input Function Outputs (Active LOW) Comparator Output Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Carry Output 1.0/3.0 1.0/3.0 1.0/4.0 1.0/1.0 1.0/5.0 50/33.3 OC (Note 1)/33.3 50/33.3 50/33.3 50/33.3
Input IIH/IIL Output IOH/IOL 20 A/-1.8 mA 20 A/-1.8 mA 20 A/-2.4 mA 20 A/-0.6 mA 20 A/-3.0 mA -1 mA/20 mA (Note 1)/20 mA -1 mA/20 mA -1 mA/20 mA -1 mA/20 mA
Functional Description
The 74F181 is a 4-bit high-speed parallel Arithmetic Logic Unit (ALU). Controlled by the four Function Select inputs (S0-S3) and the Mode Control input (M), it can perform all the 16 possible logic operations or 16 different arithmetic operations on Active HIGH or Active LOW operands. The Function Table lists these operations. When the Mode Control input (M) is HIGH, all internal carries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the Cn + 4 output, or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate). In the Add mode, P indicates that F is 15 or more, while G indicates that F is 16 or more. In the Subtract mode P indicates that F is zero or less, while G indicates that F is less than zero. P and G are not affected by carry in. When speed requirements are not stringent, the 74F181 can be used in a simple Ripple Carry mode by connecting the Carry output (Cn+4) signal to the Carry input (Cn) of the next unit. For high speed operation the device is used in conjunction with a carry lookahead circuit. One carry lookahead package is required for each group of four 74F181 devices. Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths. The A = B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the Subtract mode. The A = B output is open collector and can be wired AND with other A = B outputs to give a comparison for more than four bits. The A = B signal can also be used with the Cn+4 signal to indicate A > B and A < B. The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition (1s complement), a carry out means borrow; thus a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated, this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are performed to the operands labeled inside the logic symbol.
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74F181
Operation Table
Logic S0 L H L H L H L a. All Input Data Inverted H L H L H L H L H L H L H L H L b. All Input Data True H L H L H L H L H S1 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H S2 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H S3 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H (M=H) A A*B A+B A+B B AB A+B A*B AB B A+B Logic "0" A*B A*B A A A+B A*B Arithmetic (M=L, C0=Inactive) A minus 1 A * B minus 1 A * B minus 1 A plus (A + B) A * B plus (A + B) A minus B minus 1 A+B A plus (A + B) A plus B A * B plus (A + B) A+B A plus A (2 x A) A plus A * B A plus A * B A A A+B A+B A plus (A * B) A * B plus (A + B) A minus B minus 1 A * B minus 1 A plus A * B A plus B A * B plus (A + B) A * B minus 1 A plus A (2 x A) A plus (A + B) A plus (A + B) A minus 1 Arithmetic (M=L, C0=Active) A A*B A*B Zero A plus (A + B) plus 1 A * B plus (A + B) plus 1 A minus B A + B plus 1 A plus (A + B plus 1 A plus B plus 1 A * B plus (A + B) plus 1 A + B plus 1 A plus A (2 x A) plus 1 A plus A * B plus 1 A plus A * B plus 1 A plus 1 A plus 1 A + B plus 1 A + B plus 1 Zero A plus A * B plus 1 A * B plus (A + B) plus 1 A minus B A*B A plus A * B plus 1 A plus B plus 1 A * B plus (A + B) plus 1 A*B A plus A (2 x A) plus 1 A plus (A+B) plus 1 A plus (A+B) plus 1 A
Logic "1" minus 1 (2s comp.)
Logic "0" minus 1 (2s comp.) A*B B AB A*B A+B AB B A*B Logic "1" A+B A+B A
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74F181
Logic S0 L H L H L H L c. A All Input Data Inverted; B Input Data True H L H L H L H L H L H L H L H L d. A Input Data True; B Input Date Inverted H L H L H L H L H S1 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H S2 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H S3 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H (M=H) A A+B A*B
Arithmetic (M=L, C0=Inactive) A minus 1 A * B minus 1 A * B minus 1 A plus (A + B) A * B plus (A + B) A plus B A+B A plus (A + B) A minus B minus 1 A * B plus (A + B) A+B A plus A (2 x A) A plus A * B A plus A * B A A A+B A+B A plus A * B A * B plus (A + B) A plus B A * B minus 1 A plus A * B A minus B minus 1 A * B plus (A + B) A * B minus 1 A plus A (2 x A) A plus (A + B) A plus (A + B) A minus 1
Arithmetic (M=L, C0=Active) A A*B A*B Zero A plus (A + B) plus 1 A * B plus (A + B) plus 1 A plus B plus 1 A + B plus 1 A plus (A + B) plus 1 A minus B A * B plus (A + B) plus 1 A + B plus 1 A plus A (2 x A) plus 1 A plus A * B plus 1 A plus A * B plus 1 A plus 1 A plus 1 A + B plus 1 A + B plus 1 Zero A plus A * B plus 1 A * B plus (A + B) plus 1 A plus B plus 1 A*B A plus A * B plus 1 A minus B A * B plus (A + B) plus 1 A*B A plus A (2 x A) plus 1 A plus (A+B) plus 1 A plus (A+B) plus 1 A
Logic "1" minus 1 (2s comp.) A*B B AB A+B A+B AB B A+B Logic "0" A*B A*B A A A*B A+B A+B B AB A*B A*B AB B A*B Logic "1" A+B A+B A
Logic "0" minus 1 (2s comp.)
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74F181
Logic Diagram
p
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F181
Absolute Maximum Ratings(Note 2)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current 4.75 3.75 -0.6 -1.8 -2.4 -3.0 IOS IOHC ICCH ICCL Output Short-Circuit Current Open Collector, Output OFF Leakage Test Power Supply Current Power Supply Current 43 43 -60 -150 250 65.0 65.0 mA A mA mA Max Min Max Max mA Max 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 5.0 7.0 Min 2.0 0.8 -1.2 Typ Max Units V V V V V A A A V A Min Min Min Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC (Fn, G, P, Cn+4) IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (M) VIN = 0.5V (A0, A1, A3, B0, B1, B3) VIN = 0.5V (Sn, A2, B2) VIN = 0.5V (Cn) VOUT = 0V (Fn, G, P, Cn+4) VO = VCC (A = B) VO = HIGH VO = LOW
50
Max 0.0 0.0
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74F181
AC Electrical Characteristics
TA = +25C Symbol Parameter VCC = +5.0V CL = 50 pF Path tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Cn to Cn + 4 Propagation Delay A or B to Cn + 4 Propagation Delay A or B to Cn + 4 Propagation Delay Cn to F Propagation Delay A or B or G Propagation Delay A or B to G Propagation Delay A or B to P Propagation Delay A or B to P Propagation Delay Ai or Bi to Fi Propagation Delay Ai or Bi to Fi Propagation Delay Any A or B to Any F Propagation Delay Any A or B to Any F Propagation Delay A or B to F Propagation Delay A or B to A = B Dif Logic Dif Sum Dif Sum Dif Sum Dif Sum Any Dif Sum Mode Min 3.0 3.0 5.0 4.0 5.0 5.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 4.0 3.0 3.0 3.0 3.0 4.0 4.0 4.5 3.5 4.0 4.0 11.0 6.0 Typ 6.4 6.1 10.0 9.4 10.8 10.0 6.7 6.5 5.7 5.8 6.5 7.3 5.0 5.5 5.8 6.5 7.0 7.2 8.2 5.0 8.0 7.8 9.4 9.4 6.0 6.0 18.5 9.8 Max 8.5 8.0 13.0 12.0 14.0 13.0 8.5 8.5 7.5 7.5 8.5 9.5 7.0 7.5 7.5 8.5 9.0 10.0 11.0 11.0 10.5 10.0 12.0 12.0 9.0 10.0 27.0 12.5 TA = -55C to +125C VCC = +5.0V CL = 50 pF Min 3.0 3.0 5.0 3.5 5.0 4.0 2.5 2.5 2.5 2.5 2.5 2.5 2.5 3.0 2.5 3.0 3.0 3.0 3.0 3.0 3.5 4.0 3.5 3.0 3.5 3.0 8.0 5.5 Max 10.0 9.5 15.5 16.5 17.0 15.0 16.0 12.0 9.0 9.5 11.5 11.0 8.5 9.5 11.0 11.0 14.5 14.5 17.5 14.5 16.5 13.5 17.5 14.0 14.5 15.5 35.0 21.0 TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 3.0 3.0 5.0 4.0 5.0 5.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 4.0 3.0 3.0 3.0 3.0 4.0 4.0 4.5 3.5 4.0 4.0 11.0 6.0 Max 9.5 9.0 14.0 13.0 15.0 14.0 9.5 9.5 8.5 8.5 9.5 10.5 8.0 8.5 8.5 9.5 10.0 10.0 12.0 12.0 11.5 11.0 13.0 13.0 10.0 11.0 29.0 13.5 ns ns Units
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74F181
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide Package Number N24A
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74F181 4-Bit Arithmetic Logic Unit
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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